A conventional memory device is illustrated in FIG. 1 and is described in U.S. Pat. Nos. 6,097,644 and 6,366,509, the disclosure of which is incorporated herein by reference. The memory device is a synchronous dynamic random access memory (“SDRAM”) 10 that includes an address register 12 adapted to receive row addresses and column addresses through an address bus 14. The address bus 14 is generally coupled to a memory controller (not shown in FIG. 1). Typically, a row address is initially received by the address register 12 and applied to a row address multiplexer 18. The row address multiplexer 18 couples the row address to a number of components associated with either of two memory bank arrays 20 and 22 depending upon the state of a bank address bit forming part of the row address. The arrays 20 and 22 are comprised of memory cells arranged in rows and columns. Associated with each of the arrays 20 and 22 is a respective row address latch 26, which stores the row address, and a row decoder 28, which applies various signals to its respective array 20 or 22 as a function of the stored row address. The row address multiplexer 18 also couples row addresses to the row address latches 26 for the purpose of refreshing the memory cells in the arrays 20 and 22. The row addresses are generated for refresh purposes by a refresh counter 30 that is controlled by a refresh controller 32.
After the row address has been applied to the address register 12 and stored in one of the row address latches 26, a column address is applied to the address register 12. The address register 12 couples the column address to a column address latch 40. Depending on the operating mode of the SDRAM 10, the column address is either coupled through a burst counter 42 to a column address buffer 44, or to the burst counter 42, which applies a sequence of column addresses to the column address buffer 44 starting at the column address output by the address register 12. In either case, the column address buffer 44 applies a column address to a column decoder 48, which applies various column signals to respective sense amplifiers in associated column circuits 50 for the arrays 20 and 22.
Data to be read from one of the arrays 20 or 22 are coupled from the arrays 20 or 22, respectively, to a data bus 58 through the column circuit 50, and a read data path that includes a data output register 56. Data to be written to one of the arrays 20 or 22 are coupled from the data bus 58 through a write data path, including a data input register 60, to one of the column circuits 50 where they are transferred to one of the arrays 20 or 22, respectively. A mask register 64 may be used to selectively alter the flow of data into and out of the column circuits 50 by, for example, selectively masking data to be read from the arrays 20 and 22.
The above-described operation of the SDRAM 10 is controlled by a command decoder 68 responsive to high level command signals received on a control bus 70. These high level command signals, which are typically generated by the memory controller, are a clock enable signal CKE*, a clock signal CLK, a chip select signal CS*, a write enable signal WE*, a row address strobe signal RAS*, and a column address strobe signal CAS*, where the “*” designates the signal as active low. The command decoder 68 generates a sequence of command signals responsive to the high level command signals to carry out a function (e.g., a read or a write) designated by each of the high level command signals. These command signals, and the manner in which they accomplish their respective functions, are conventional. Therefore, in the interest of brevity, a further explanation of these control signals will be omitted.
A portion of the column circuits 50 of FIG. 1 is shown in greater detail in FIG. 2. The column circuit 50 is shown connected to a pair of arrays 100, 102, which may be sub-arrays in either of the arrays 20, 22 shown in FIG. 1. Alternately, a single column circuit 50 containing the circuitry shown in FIG. 2 may be used to access both of the arrays 20, 22 shown in FIG. 1. The column circuit 50 includes a plurality of column node circuits 110a-n in addition to a redundant column node circuit 112. All of these column node circuits 110, 112 are identical, and, in the interest of clarity and brevity, the internal components of only one column node circuit 110a is shown in FIG. 2.
In FIG. 2, the column node circuit 110a interfaces with two columns of memory cells using two pairs of complementary digit lines D0, D0* and D1, D1*, respectively. However, it will be understood that the column node circuit 110a may contain fewer or greater numbers of complementary digit line pairs. In the interest of brevity, the digit lines D0, D0* and D1, D1* in the column node circuit 110 as well as in the other column node circuits 110b-n and 112 will sometimes be referred to as simply D and D*. Each digit line pair D, D* has coupled therebetween a negative sense amplifier 120, a positive sense amplifier 122, an equilibration circuit 124, and an I/O circuit 126.
The equilibration circuit 124 is controlled by a pre-charge control circuit 130 that may be part of the row decoder control 28 (FIG. 1) to couple the digit lines D, D* to each other and to an equilibration voltage DVC2, which typically has a magnitude equal to one-half the magnitude of a supply voltage VCC. A typical two transistor equilibration circuit includes a first n-channel transistor coupled between digit line D and equilibration voltage DVC2 and a second n-channel transistor coupled between digit line D* and equilibration voltage DVC2. The gate electrodes of both n-channel transistors are coupled to control signal EQ. When control signal EQ from pre-charge control circuit 130 pulses high (e.g., to VCC), the two n-channel transistors of equilibration circuit 124 turn on, and charge flows between digit lines D, D* and equilibration voltage DVC2. Equilibration voltage DVC2 supplies or removes charge from both digit lines until the voltage on both digit lines D and D* is equal to DVC2. Persons of ordinary skill in the art will appreciate that a variant of the two transistor equilibration circuit is three n-channel equilibration circuit where the third n-channel transistor is coupled between the two digit lines, and a gate electrode of the third transistor is coupled to control signal EQ. This third transistor assists in speeding the equilibration between the voltages on the two digit lines. All three n-channel transistors of equilibration circuit 124 turn on, and charge flows between digit lines D, D* and equilibration voltage DVC2. Here to, equilibration voltage DVC2 supplies or removes charge from both digit lines until the voltage on both digit lines D and D* is equal to DVC2. After equilibration, control signal EQ pulses low again (e.g., ground), and all three n-channel transistors of equilibration circuit 124 turn off.
FIG. 2 depicts a typical sense amplifier that includes the negative sense amplifier 120 and the positive sense amplifier 122. When both parts of the sense amplifier are enabled, the sense amplifier operates as a latch made up of two cross coupled CMOS inverters. Typically during equilibration the sense amplifier is deactivated so as to avoid sourcing or draining any current to or from the digit lines. When the EQ signal pulses high (e.g., to VCC), current flows between the digit lines and DVC2 until both the digit lines are pre-charged to DVC2.
FIG. 3 shows a portion of the memory arrays 100, 102 of FIG. 2. The array portion includes two pairs of complementary digit lines D, D*. Each of the digit lines D, D* is coupled through respective access transistor 160 to one plate of alternating storage capacitors 162. The other plate of each storage capacitor 162 is a “cell plate” that is typically coupled to a voltage DVC2 having a magnitude of one-half of the supply voltage (e.g., VCC/2). The access transistors 160 and storage capacitors 162 are arranged in rows and columns. The access transistors 160 in each column are coupled to a respective pair of digit lines D, D*, and the gate electrodes of the access transistors 160 in each row are connected to a respective word line ROW 1, ROW 2 . . . ROW N. In operation, the storage capacitors 162 store voltages indicative of either a logic “0” or a logic “1”. After the digit lines D, D* have been equilibrated by the equilibration circuit 124 (FIG. 2), an imbalance of the voltage on the digit lines is created by turning on the access transistors 160 in an addressed row of memory cells to couple the storage capacitors (162, FIG. 3) in that row onto one, but not both, digit lines for each column. The digit line coupled to a storage capacitor 162 in each column is called the active digit line, and the other digit line is called the reference digit line. If the storage capacitor 162 coupled to the digit line D were charged to a voltage greater than DVC2 (i.e., a 1's condition), the charge on the storage capacitor 162 will increase the voltage on the active digit line to be greater than the voltage on the reference digit line. Conversely, if the storage capacitor 162 coupled to the digit line D were charged to a voltage less than DVC2 (i.e., a 0's condition), the lack of charge on the storage capacitor will decrease the voltage on the active digit line to be less than the voltage on the reference digit line. The charge stored on the capacitors 162 coupled to the complementary digit line D* is the opposite of that explained above. Specifically, a “1” stored on the storage capacitor 162 coupled to a complementary digit line D* is discharged to zero volts, and a “0” stored on the storage capacitor 162 coupled to a complementary digit line D* is charged to VCC.
After the charge on the storage capacitor 162 has been coupled to the active digit line, the sense amplifier is turned on. An imbalance in the digit lines is enhanced by the sense amplifier, and the latch effect of the sense amplifier is enabled so as to drive the digit lines D, D* in the direction of the imbalance until one of the digit lines is at the supply voltage and the other of the digit lines is at ground potential. In this way, the sense amplifiers 120, 122 detect a voltage imbalance in the digit lines D, D* during a read access of memory cells in the arrays 100, 102. The access transistors 160 coupled to an active row line remain ON during the time the sense amplifiers 120, 122 drive to digit lines to the supply voltage and ground potential. As a result, the storage capacitors 162 in the active row are recharged or to their original value or “refreshed” in they event they were internally discharged by leakage currents.
Once the sense amplifiers 120, 122 have driven the digit lines D, D* to voltages indicative of the data read from a memory cell in the respective column, the digit lines D0, D0* are coupled to respective I/O lines I/OA, I/OA* by the I/O circuit 126 (see FIG. 2). As is a well understood in the art, in a read memory access, the signals from the digit lines are coupled to a DC sense amplifier, which applies a corresponding data signal to the data bus of the memory device. The other digit lines D1, D1* in the column node circuit 110a are similarly coupled to a respective pair of I/O lines I/OB, I/OB* by a respective I/O circuit 126.
In a write memory access, the I/O lines are driven by respective write drivers (not shown), and are coupled to the digit lines D, D* by the I/O circuit 126.
The column node circuit 110a receives a SEL_R signal from a respective inverter 114 to cause it to couple its digit lines D, D* to the I/O lines I/O, I/O*, respectively. Similarly, the column node circuit 110b receives a SEL_R+1 signal to couple its digit lines to the same I/O lines, and the column node circuit 110n receives a SEL_R+N signal to couple its digit lines to the same I/O lines. Since the SEL signals select various columns of memory cells in the arrays 100, 102, they are normally generated by the column decoder 48 (FIG. 1).
The I/O circuits 126 in the redundant column node circuit 112 are likewise coupled to the same 1/0 lines by a select SEL_RED signal, but the SEL_RED signal is generated by a redundant column control circuit 144. The redundant column control circuit 144 may be part of the column decoder 48 (FIG. 1).
As mentioned above, the column node circuits 110a-n and 112 are coupled to both arrays 100, 102. However, the column node circuits cannot receive signals indicative of read data from both arrays 100, 102 at the same time. For this reason, isolation transistors 150, 152 are often coupled between each digit line D, D* of the column node circuit and corresponding digit lines D, D*, respectively, of the arrays 100, 102. All of the isolation transistors 150 coupled to the array 100 are turned ON by a common ISO_LEFT signal, and all of the isolation transistors 152 coupled to the array 102 are turned ON by a common ISO_RIGHT signal. Since the arrays 100, 102 contain rows of memory cells corresponding to different row addresses, the ISO_LEFT and ISO-RIGHT signals are typically generated by the row decoder control 28 (FIG. 1).
Although the manufacturing yield of memory devices is very good, the large number of transistors, signal paths, and other components, such as capacitors, contained in memory devices creates a significant statistical probability that a memory device will contain at least one defective transistor, signal path or other component. For this reason, memory devices typically incorporate rows and columns of redundant memory cells. If a row or column of memory cells is found to be defective during testing, either before or after packaging the memory device, the memory device can be programmed to substitute a redundant row of memory cells for the defective row, or a redundant column of memory cells for the defective column. The redundant column node circuit 112 is provided to interface with redundant columns of memory cells in the arrays 100, 102. The redundant column node circuit 112 interfaces with two columns of memory cells, so that two redundant columns are substituted whenever a single defective column is found during testing. However, it will be understood that redundant columns can be substituted on a column-by-column basis, or that redundant columns can be substituted in groups larger than two. The number of digit lines D, D* in the redundant column node circuit 112 can be adjusted as desired to match the number of redundant columns that are substituted.
Such memory devices include one or more arrays of memory cells arranged in rows and columns. Each array may be divided into several sub-arrays. Typically, one or more digit or “bit” line is provided for each column of the array, and each digit line is coupled to a respective sense amplifier. Each sense amplifier is generally a differential amplifier that compares the voltage at one of its inputs to the voltage at the other of its inputs. The sense amplifier then drives its inputs to complementary logic levels corresponding to the sensed differential voltage.
There are currently two principal array architectures that are commonly used in memory devices, such as DRAMs: a folded digit line architecture and an “open-array” architecture. In an “open-array” architecture, the complementary digit lines span two adjacent sub-arrays, and each digit line is coupled to each memory cell in a respective column. A sense amplifier is coupled to the digit lines of two adjacent sub-arrays. Thus, each sense amplifier is shared by two sub-arrays so that one input to the sense amplifier is coupled to the digit line of one array and the other input to the sense amplifier is coupled to the digit line of the other array. Prior to a memory read operation, the digit lines are pre-charged to a voltage that is typically one-half the supply voltage, a voltage known as DVC2.
In response to a memory read operation, one of the digit lines coupled to a sense amplifier is coupled to a memory cell being read. In response, the voltage on the digit line either increases or decreases from DVC2 depending upon the logic level stored in the memory cell. The other digit line remains at the pre-charge voltage, DVC2. The sense amplifier detects that the voltage on the digit line coupled to the memory cell being read has either increased or decreased relative to the pre-charge voltage and then drives the digit lines to complementary logic levels corresponding to the sensed voltage.
The other architecture that is commonly used in memory device arrays is the folded digit line architecture, which is shown in FIG. 2 and was previously explained. In a folded digit line architecture, each column is provided with a pair of complementary digit lines, and the digit lines of each pair are generally coupled to alternate memory cells in the same sub-array. The complementary digit lines are coupled to the inputs of a respective sense amplifier. Thus, the digit lines coupled to each sense amplifier are from the same sub-array. A memory read operation in a folded digit line architecture was previously explained with reference to FIG. 2, and is essentially the same as in an open-array architecture.
Each of the above-described architectures has its advantages and disadvantages. A disadvantage of the open-array architecture relative to the folded digit line architecture is that it is susceptible to errors resulting from noise because each sense amplifier input is coupled to a different array. In contrast, since both digit lines coupled to a sense amplifier in a folded digit line architecture extend closely adjacent each other through the same array, they tend to pick up the same noise signals. The differential operation of the sense amplifiers thus makes them insensitive to these common mode noise signals.
Although folded digit line architectures have better noise immunity, they have a significant disadvantage compared to open-array architectures in that they are less efficient. Due to the nature of the layout of a folded architecture, each memory cell occupies 8F2 in area, where “F” is the minimum feature size of the semiconductor process. The layout of an open array architecture allows for a 6F2 cell area, thereby resulting in a 25% reduction over the 6F2 cell. Thus, open-array architectures are theoretically substantially more efficient than folded digit line architectures in using the surface area of a semiconductor die.
The drain and source of each access transistor 160 are typically formed by N type implant regions in a P type substrate, and the substrate generally is coupled to a potential of 0 volts (i.e., ground) or most times a negative voltage. The N type implant region of transistor 160 that is coupled to capacitor 162 forms a diode junction with the P type substrate.
When a logic “0” is stored on capacitor 162, the N type implant region of transistor 160 that is coupled to capacitor 162 will be charged to a potential of 0 volts (i.e., ground), and the voltage difference across the diode junction is zero volts, assuming the P type substrate is also coupled to a potential of 0 volts (i.e., ground). However, when a logic “1” is stored on capacitor 162, the N type implant region of transistor 160 that is coupled to capacitor 162 will be charged to a potential of +VCC volts (i.e., the supply voltage), and the voltage difference across the diode junction is therefore VCC volts. Although the diode junction is back biased it nevertheless passes a small amount of leakage current. Eventually, charge leakage from a storage capacitor 162 will cause the potential on the capacitor to decay until, what was once a logic “1”, will appear as a logic “0”. Before this point in time, the charge on the capacitor is refreshed during normal operation. As previously explained, a refresh cycle involves activating a word line to couple the voltage on the capacitor to a sense amplifier (before the capacitor's potential decays sufficiently to loose data). Each sense amplifier then drives the respective pair of digit lines D, D*, and a digit line is driven to VCC for a cell that is to store a logic “1” to recharge the storage capacitor 162 in the active row. Each refresh cycle consumes a discrete quantity of energy. Since the refresh cycles are repeated sufficiently often to avoid data loss, the loss of the discrete quantity of energy also repeats at the same rate. This translates into power consumed by the memory device.
The power consumed by integrated circuits can be a critical factor in their utility in certain applications. For example, the power consumed by memory devices used in portable personal computers greatly affects the length of time they can be used without the need to recharge batteries powering such computers. Power consumption can also be important even where memory devices are not powered by batteries because it may be necessary to limit the heat generated by the memory devices.
In general, memory device power consumption increases with both the capacity and the operating speed of the memory devices. The power consumed by memory devices is also affected by their operating mode. A dynamic random access memory (“DRAM”), for example, will generally consume a relatively large amount of power when the memory cells of the DRAM are being refreshed because rows of memory cells in a memory cell array are then being actuated in the rapid sequence. Each time a row of memory cells is actuated, a pair of digit lines for each memory cell are switched to complementary voltages and then equilibrated, thereby consuming a significant amount power. As the number of columns in the array increases with increasing memory capacity, the power consumed in actuating each row increases accordingly. Power consumption also increases with increases in the rate at which the rows of memory cells are actuated. Thus, as the speed and capacity of DRAMs continue to increase, so also does the power consumed increase during refresh of memory cells in such DRAMs.
As the use of electronic devices, such as personal computers, continue to increase, it is becoming ever more important to make such devices portable. The usefulness of portable electronic devices, such as notebook computers, is the limited by the limited length of time batteries are capable of powering the device before needing to be recharged. This problem has been addressed by attempts to increase battery life and attempts to reduce the rate at which such electronic devices consume power.
Various techniques have been used to reduce power consumption in electronic devices, the nature of which often depends upon the type of power consuming electronic circuits that are in the device. For example, electronic devices, such a notebook computers, typically include dynamic random access memory (“DRAM”) devices that consume a substantial amount of power. As the data storage capacity and operating speeds of DRAM devices continues to increase, the power consumed by such devices has continued to increase in a corresponding manner.
One technique that has been used to reduce the amount of power consumed by refreshing DRAM memory cells is to vary the refresh rate as a function of temperature. As is well known in the art, the rate at which charge leaks from a DRAM memory cell increases with temperature. The refresh rate must be sufficiently high to ensure that no data is lost at the highest temperature in the specified range of operating temperatures of the DRAM device. Yet, DRAM devices normally operate at a temperature that is substantially lower than their maximum operating temperature. Therefore, DRAM devices are generally refreshed at a rate that is higher than the rate actually needed to prevent data from being lost, and, as a result, unnecessarily consume power. To address this problem, some commercially available DRAM devices allow the user to program a mode register to select a lower maximum operating temperature. The DRAM device then adjusts the refresh rate to correspond to the maximum operating temperature selected by the user.
Although adjusting the refresh rate as a function of temperature does reduce the rate of power consumed by refresh, it nevertheless still allows power to be consumed at a significant rate for several reasons. For example, although the refresh rate may be reduced with reduced maximum operating temperature, the refresh may still result in refreshing a large number of memory cells that are not actually storing data.
Another approach to reducing the rate at which power is consumed by a refresh operation is to refresh less than all of the memory cells in the DRAM device in attempt to refresh only those memory cells needed to store data for a given application. As described in U.S. Pat. No. 5,148,546 to Blodgett, incorporated herein by reference, a software program being executed in a computer system containing the DRAM devices is analyzed to determine the data storage requirements for the program. The DRAM device is then refreshed only those rows of memory cells that are needed to store data.
In another approach, the DRAM device may be operated in a partial array self refresh (“PASR”) mode. In the PASR mode, a mode register is programmed by a user to specify a bank or portion thereof of memory cells that will be used and thus must be refreshed. The remaining memory cells are not used and thus need not be refreshed during at least some refresh modes. Although these techniques for refreshing less than all of the memory cells in a memory device can substantially reduce the rate of power consumption, it can nevertheless require a substantial amount of power to refresh the cells that are to be refreshed.
Still another technique that can be used to reduce the rate of refresh involves operating DRAM devices in a half density mode. A DRAM device that may be operated in a half density mode is described in U.S. Pat. No. 5,781,483 to Shore, incorporated herein by reference. In the half density mode, the low order bit of each row address, which normally designates whether the addressed row is even or odd, is ignored, and both the odd row and adjacent even row are addressed for each memory access. In a folded digit line architecture, activating an odd row will couple each memory cell in the row to a respective digit line, and activating an even row will couple each memory cell in the row to a respective complementary digit line. Thus, for example, writing a “1” to an addressed row and column would result in writing a logic “1” voltage level to the memory cell in the addressed odd row and writing a logic “0” logic level to the memory cell in the addressed even row. Reading from the addressed row and column results in a logic “1” voltage level being applied to the digit line for the addressed column and a logic “0” voltage level being applied to the complementary digit line for the addressed column. Therefore, in the half density mode, a sense amplifier coupled to the digit line and complementary digit line for each column receives twice the differential voltage that it normally receives when reading a memory cell at an addressed row and column.
The half density mode can be used to reduce that rate at which power is consumed during refresh. Although a refresh in the half density mode requires twice as many memory cells to be refreshed for a given amount of stored data, the required refresh rate is less than half the required refresh rate when the DRAM device is operating in the full density mode. The substantially lower refresh rate required in the half density results from the increased differential voltage that is applied to the sense amplifiers in the half density mode, as previously explained. As a result, the memory cells can be allowed to discharge to a greater degree between refreshes without the data bits stored therein being lost. Therefore, storing data in the half density mode can reduce the rate of power consumption during refresh.
Although these problems have been explained with reference to the SDRAM 10 shown in FIG. 1, it will be understood that the same problems exist with other dynamic random access memories (“DRAMs”) including asynchronous DRAMs and packetized DRAMs, such as synchronous link DRAMs (“SLDRAMs”) and RAMBUS DRAMs (“RDRAMs”).
All of the above techniques are at least somewhat effective in reducing the required refresh rate of DRAMs. However, they do not provide optimum results because, whatever technique is used, it is still necessary to refresh the storage capacitors before the charge on the capacitors has changed to the point where data read errors might occur. If some means could be devised to increase the time that could lapse before it was necessary to recharge the storage capacitors, the power saved by virtually all of the above-described techniques could be further increased. There is therefore a need for a method and apparatus that can be used to extend the time between refresh cycles without loss of data which does not unduly increase the cost or power consumption of memory devices.